1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device for which a dual damascene method is adopted.
2. Description of the Related Art
With the recent progress of high-density design of a semiconductor integrated circuit, density of a wiring pattern has increased, and a wiring has become longer. Al was conventionally used for a wiring material; however, wiring delay has come up as a problem with the miniaturization of the wiring pattern. Recently, Cu is mainly used as the wiring material in order to solve the problem. However, it is difficult to transfer the wiring pattern on the Cu itself unlike the Al. Therefore, when a Cu wiring is formed, a damascene method for transferring a wiring trench pattern on an interlayer dielectric and for forming the wiring pattern thereon by embedding the Cu is effective. Furthermore, the damascene method is classified into a single damascene method for separately forming the Cu in a trench and the Cu in a via, and a dual damascene method for simultaneously forming the trench and the via.
Meanwhile, in order to solve the problem of the wiring delay, a low dielectric constant film having lower dielectric constant than a conventional oxide film is used as a material for the interlayer dielectric. The material of the low dielectric constant film is classified broadly into two kinds: an inorganic material and an organic material. Generally, they are used appropriately in order to satisfy a demand of characteristics of each device.
A Cu dual damascene method is preferably used for configuring a wiring layer of a semiconductor device in a generation of 130 nm nodes and below. Furthermore, when an organic low dielectric constant film is used as the interlayer dielectric, a trench-first hard mask method is generally used for an interlayer structure. Here, the trench-first hard mask method means a method for forming a hard mask pattern for forming the wiring trench pattern on the interlayer dielectric in advance, then patterning the via directly on a level difference of the wiring trench pattern, and then processing the via and processing the trench in the interlayer dielectric in this order, thereby forming a dual damascene structure.
Prior arts are described in Japanese Patent Laid-open No. 2001-351976 and Japanese Patent Laid-open No. 2000-124306.
An ArF excimer laser is generally used for exposing the via pattern in the generation of 100 nm nodes and below. However, with the miniaturization of the pattern, an error of the pattern formed by the ArF excimer laser has become beyond the limit of what is acceptable.